This invention relates to an improved, low power sense amplifier for a programmable logic device (PLD) which utilizes an electrically programmable, read-only memory (EPROM) as the storage cell at each "intersection" of the array.
Programmable logic devices using EPROM storage cells are well known. Their operation and structure have been described in the literature and in patents. For example, U.S. Pat. Nos. 4,124,899; 4,609,986 and 4,617,479 and the references cited in those patents describe such arrays. Further information is contained on pages 4-1 through 4-61 of CMOS Data Book of Cypress Semiconductor Corporation, 3901 N. First Street, San Jose, Calif. 95134.
Recent advances in sensing techniques for PLDs include the use of a reference voltage generator and clamp to reduce the voltage swings on the product term lines. Using such a reference voltage generator and clamp, when the PLD circuit is powered up, the voltage at the output of the reference voltage generator, connected to the product term line, converges near the trip paint of the sense amplifier rather than near the rail voltage of the CMOS devices. This reduces the amount by which the product term line must be pulled during sensing. However, since the reference voltage generator maintains the product term line at a higher voltage than where it would otherwise be, the circuit requires more DC power.
Because of the added power requirements of these advanced sense amplifiers, a need arises for new techniques to reduce power consumption. The sense amplifiers draw 70 to 80 percent of the power used in a PLD. The circuit of this invention provides a sense amplifier with substantially reduced power consumption.